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Wireless Components
ASK/FSK Single Conversion Receiver TDA 5211 Version 2.0
Specification May 2001
Revision History Current Version: 2.0 as of 18.05.01 Previous Version: 1.1, Dec. 2000 Page (in previous Version) 3-12 4-4 4-13 5-3 5-4 5-5 5-6 5-7 5-9 Page (in current Version) 3-12 4-4 4-13 5-3 5-4 5-5 5-6 5-7 5-9 Subjects (major changes since last revision)
Sec. 3.4.8: max. datarate changed, Sec. 3.4.9: max. output current changed value of a changed to 1.414 value for C2 changed to 22nF according to bill of materials, 2 and T2 changed min. supply current limits added, max. limits changed supply current max. limit changed, min. limit added 3VOUT min. & max. limits changed, TAGC typ. & max. values changed Section "SLICER" reworked, max. datarate at given load capacitance quoted, high output voltage limits changed, precharge current: min., max. limits changed PDO load and leakage currents limits and typ. values changed, FSK demodulation gain min. limit changed PDWN-current max. limit changed, supply currents min. limits added, max. limits changed, 3VOUT min. & max. limits changed, ITAGC_out limits changed Section "SLICER" reworked, max. datarate at given load capacitance quoted, high output voltage limits changed, precharge current: min., max. limits changed, PDO output voltage removed C18 value changed
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5-10
5-15
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TDA 5211
Product Info
Product Info
General Description The IC is a very low power consump- Package tion single chip FSK/ASK Superheterodyne Receiver (SHR) for the frequency band 310 to 350 MHz that is pin compatible with the ASK Receiver TDA5201. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
s
Features
Low supply current (Is = 5.7 mA typ. in FSK mode, Is = 5 mA typ. in ASK mode) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ.) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser ASK sensitivity better than -110 dBm over specified temperature range (- 40 to +105C)
s
Selectable frequency ranges 310330 MHz and 330-350 MHz Limiter with RSSI generation, operating at 10.7MHz Selectable reference frequency 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold FSK sensitivity better than -102 dBm over specified temperature range (- 40 to +105C)
s
s s
s s
s
s
s
s
s
Applications
s s
Keyless Entry Systems Remote Control Systems
s s
Alarm Systems Low Bitrate Communication Systems
Ordering Information
Type TDA 5211 samples available Ordering Code Q67037-A1147 Package P-TSSOP-28-1
Wireless Components
Product Info
Specification, May 2001
1
2.1 2.2 2.3 2.4
Table of Contents
i
1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 2 2 3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 3 9 9 9 10 10 10 11 11 12 12 12 12
3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 FSK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.8 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.9 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.10 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 4.2 4.3 4.4 4.5 4.6 Choice of LNA Threshold Voltage and Time Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 4 5 6 7 8 8 10 11
4.6.1 FSK Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 ASK Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 2 3 4 9 12 13 15 17
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 AC/DC Characteristics at TAMB = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.4 AC/DC Characteristics at TAMB = -40 to 105C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 5.3 5.4 5.5 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix - Noise Figure and Gain Circles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Product Description
Contents of this Chapter 2.1 2.2 2.3 2.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
TDA 5211
Product Description
2.1 Overview
The IC is a very low power consumption single chip FSK/ASK Superheterodyne Receiver (SHR) for receive frequencies between 310 and 350 MHz that is pin compatible to the ASK Receiver TDA5201. The IC offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a PLL FSK demodulator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life.
2.2 Application
s s s s
Keyless Entry Systems Remote Control Systems Alarm Systems Low Bitrate Communication Systems
2.3 Features
s s s s s s
Low supply current (Is = 5.7 mA typ.FSK mode, 5mA typ. ASK mode) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ.) FSK and ASK demodulation capability Fully integrated VCO and PLL Synthesiser RF input sensitivity ASK -113dBm typ. at 25C, better than -110dBm over complete specified operating temperature range (-40 to +105C) RF input sensitivity FSK -105dBm typ. at 25C, better than -102dBm over complete specified operating temperature range (-40 to +105C) Receive frequency range between 310 and 350 MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold
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s s s s s
Wireless Components
2-2
Specification, May 2001
TDA 5211
Product Description
2.4 Package Outlines
P_TSSOP_28.EPS
Figure 2-1
P-TSSOP-28-1 package outlines
Wireless Components
2-3
Specification, May 2001
3
Functional Description
Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
TDA 5211
Functional Description
3.1 Pin Configuration
CRST1 VCC LNI TAGC AGND LNO VCC MI M IX AGND FSEL IF O DGND VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
CRST2 PDW N PDO DATA 3VO UT THRES FFB OPP SLN SLP L IM X L IM CSEL M SEL
TDA 5211
22 21 20 19 18 17 16 15
Pin_Configuration_5211.wmf
Figure 3-1
IC Pin Configuration
Wireless Components
3-2
Specification, May 2001
TDA 5211
Functional Description
3.2 Pin Definition and Function
In the subsequent table the internal circuits connected to the pins of the device are shown. ESD-protection circuits are omitted to ease reading. .
Table 3-1 Pin Definition and Function Pin No. 1 Symbol CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1
4 .1 5 V
1
50uA
2 3
VCC LNI
5V Supply LNA Input
57uA
3
500uA 4k
1k
Wireless Components
3-3
Specification, May 2001
TDA 5211
Functional Description
4
TAGC
4 .3V
AGC Time Constant Control
3u A 4
1k
1.4 uA
1.7V
5 6
AGND LNO
5V
Analogue Ground Return LNA Output
1k
6
7 8
VCC MI
1.7 V
5V Supply Mixer Input
2k
2k
9
MIX
8 9
Complementary Mixer Input
4 0 0 uA
10 11
AGND FSEL
Analogue Ground Return not applicable - has to be left open
Wireless Components
3-4
Specification, May 2001
TDA 5211
Functional Description
12
IFO
10.7 MHz IF Mixer Output
300uA
2 .2 V
60 12
4 .5 k
13 14 15
DGND VDD MSEL
Digital Ground Return 5V Supply (PLL Counter Circuitry) ASK/FSK Modulation Format Selector
1.2V
3.6k 15
16
CSEL
6.xx or 13.xx MHz Quartz Selector
1 .2 V
8 0k 16
Wireless Components
3-5
Specification, May 2001
TDA 5211
Functional Description
17
LIM
2 .4 V
Limiter Input
15k 17
Complementary Limiter Input 18 LIMX
330 75uA
18
15k
19
SLP
Data Slicer Positive Input
15uA
100 19
3k
8 0 A
20
SLN
Data Slicer Negative Input
5uA
10k 20
21
OPP
OpAmp Noninverting Input
5uA
20 0 21
Wireless Components
3-6
Specification, May 2001
TDA 5211
Functional Description
22
FFB
Data Filter Feedback Pin
5u A
10 0k 22
23
THRES
AGC Threshold Input
5uA
10k 23
24
3VOUT
24 2 0k 3 .1 V
3V Reference Output
25
DATA
Data Output
500 25 40k
Wireless Components
3-7
Specification, May 2001
TDA 5211
Functional Description
26
PDO
Peak Detector Output
200 26
27
PDWN
27
Power Down Input
220k
220k
28
CRST2
External Crystal Connector 2
4 .1 5V
28
50 uA
Wireless Components
3-8
Specification, May 2001
TDA 5211
Functional Description
3.3 Functional Block Diagram
VCC
IF Filter
MSEL LNO 6 MI 8 MIX 9 IFO 12 LIM 17 LIMX 18 15 FFB 22 OPP 21 SLP 19 SLN 20
LNI
RF
3
LNA
+
OP LIMITER FSK PLL Demod
TAGC
4 PEAK 26 PDO DETECTOR
OTA
TDA 5211
: 128 / 64 DET CRYSTAL OSC UREF AGC Reference
:1/2 VCC 14
VCO
DGND 13 2,7 5,10 11
Loop Filter 16 1 28
VCC AGND
(FSEL)
CSEL Crystal
Figure 3-2
Main Block Diagram
3.4 Functional Blocks
3.4.1
Low Noise Amplifier (LNA)
The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 3dB, the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be deter-
Wireless Components
3-9
-
+ FSK - ASK +
SLICER +
25
DATA
23
THRES
24
3VOUT
Bandgap Reference 27
PDWN
Functional_diagram_5211.wmf
Specification, May 2001
TDA 5211
Functional Description
mined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operating case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1.
3.4.2
Mixer
The Double Balanced Mixer downconverts the input frequency (RF) in the range of 310-350MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB by utilising either high- or low-side injection of the local oscillator signal. In case the mixer is interfaced only single-ended, the unused mixer input has to be tied to ground via a capacitor. The mixer is followed by a low pass filter with a corner frequency of 20MHz in order to suppress RF signals to appear at the IF output (IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330 to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry.
3.4.3
PLL Synthesizer
The Phase Locked Loop synthesizer consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. The FSEL pin (Pin11) has to be left open. The tuning range of the VCO was designed to guarantee over production spread and the specified temperature range a receive frequency range between 310 and 350MHz depending on whether high- or low-side injection of the local oscillator is used. The oscillator signal is fed both to the synthesiser divider chain and to a divider that is dividing the signal by 2 before it is applied to the downconverting mixer. Local oscillator high side injection has to be used for receive frequencies between approximately 310 and 330 MHz, low side injection for receive frequencies between 330 and 350MHz - see also Section 4.4..
3.4.4
Crystal Oscillator
The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 5 and 10MHz range as the overall division ratio of the PLL can be switched between 32 and 64 via the CSEL (Pin 16 ) pin according to the following table.
Table 3-2 CSEL Pin Operating States CSEL Open Shorted to ground Crystal Frequency 5.xx MHz 10.xx MHz
Wireless Components
3 - 10
Specification, May 2001
TDA 5211
Functional Description
The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is explained in Section 4.4.
3.4.5
Limiter
The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80 dB that has a bandpass-characteristic centred around 10.7 MHz. It has a typical input impedance of 330 to allow for easy interfacing to a 10.7 MHz ceramic IF filter. The limiter circuit also acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4-2. This signal is used to demodulate ASK-modulated receive signals in the subsequent baseband circuitry. The RSSI output is applied to the modulation format switch, to the Peak Detector input and to the AGC circuitry. In order to demodulate ASK signals the MSEL pin has to be left open as described in the next chapter.
3.4.6
FSK Demodulator
To demodulate frequency shift keyed (FSK) signals a PLL circuit is used that is contained fully on chip. The Limiter output differential signal is fed to the linear phase detector as is the output of the 10.7 MHz center frequency VCO. The demodulator gain is typically 140V/kHz. The passive loop filter output that is comprised fully on chip is fed to both the VCO and the modulation format switch described in more detail below. This signal is representing the demodulated signal with low frequencies applied to the demodulator demodulated to logic ones and high frequencies demodulated to logic zeroes. However this is only valid in case the local oscillator is low-side injected to the mixer which is applicable to receive frequencies above 330MHz (e.g. 345MHz). In case of receive frequencies below 330MHz (e.g.315MHz) high frequencies are demodulated as logical ones due to a sign inversion in the downconversion mixing process. See also Section 4.4. The modulation format switch is actually a switchable amplifier with an AC gain of 11 that is controlled by the MSEL pin (Pin 15) as shown in the following table. This gain was chosen to facilitate detection in the subsequent circuits. The DC gain is 1 in order not to saturate the subsequent Data Filter wih the DC offset produced by the demodulator in case of large frequency offsets of the IF signal. The resulting frequency characteristic and details on the principle of operation of the switch are described in Section 4.6.
Table 3-3 MSEL Pin Operating States MSEL Open Shorted to ground Modulation Format ASK FSK
Wireless Components
3 - 11
Specification, May 2001
TDA 5211
Functional Description
The demodulator circuit is switched off in case of reception of ASK signals.
3.4.7
Data Filter
The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100k on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2.
3.4.8
Data Slicer
The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of up to 100kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for sbsequent circuits. The self-adjusting threshold on pin 20 its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4.5.
3.4.9
Peak Detector
The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An external RC network is necessary. The input is connected to the output of the RSSI-output of the Limiter, the output is connected to the PDO pin (Pin 26 ). This output can be used as an indicator for the received signal strength to use in wake-up circuits and as a reference for the data slicer in ASK mode. The output current is typically 950A, the discharge current is lower than 2A. Note that the RSSI level is also output in case of FSK mode.
3.4.10
Bandgap Reference Circuitry
A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA.
Table 3-4 PDWN Pin Operating States PDWN Open or tied to ground Tied to Vs Operating State Powerdown Mode Receiver On
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3 - 12
Specification, May 2001
4
Applications
Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Choice of LNA Threshold Voltage and Time Constant . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 ASK/FSK Switch Functional Description . . . . . . . . . . . . . . . . . . . . . . 4-8 Principle of the Precharge Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
TDA 5211
Applications
4.1 Choice of LNA Threshold Voltage and Time Constant
In the following figure the internal circuitry of the LNA automatic gain control is shown.
R1
R2
Uth re s h old Pins: 24 23
20k
RSSI (0.8 - 2.8V)
OTA +3.1 V
VCC
Ilo a d RSSI > Uth r es h o ld : Ilo a d =4.2A RSSI < Uth r es h o ld : Ilo a d = -1.5A 4 UC C Gain control voltage
LNA
Uc :< 2.6V : Gain high Uc :> 2.6V : Gain low Uc ma x = VC C - 0.7V Uc min = 1.67V
LNA_autom.wmf
Figure 4-1
LNA Automatic Gain Control Circuitry
The LNA automatic gain control circuitry consists of an operational transimpedance amplifier that is used to compare the received signal strength signal (RSSI) generated by the Limiter with an externally provided threshold voltage Uthres. As shown in the following figure the threshold voltage can have any value between approximately 0.8 and 2.8V to provide a switching point within the receive signal dynamic range. This voltage Uthres is applied to the THRES pin (Pin 23) The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin. If the RSSI level generated by the Limiter is higher than Uthres, the OTA generates a positive current Iload. This yields a voltage rise on the TAGC pin (Pin 4). Otherwise, the OTA generates a negative current. These currents do not have the same values in order to achieve a fast-attack and slow-release action of the AGC and are used to charge an external capacitor which finally generates the LNA gain control voltage.
Wireless Components
4-2
Specification, May 2001
TDA 5211
Applications
LNA always in high gain mode
3
2.5
UTHRES Voltage Range
2
RSSI Level Range
RSSI Level
1.5
1
LNA always in low gain mode
0.5
0 -120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Input Level at LNA Input [dBm]
RSSI-AGC.wmf
Figure 4-2
RSSI Level and Permissive AGC Threshold Levels
The switching point should be chosen according to the intended operating scenario. The determination of the optimum point is described in the accompanying Application Note, a threshold voltage level of 1.8V is apparently a viable choice. It should be noted that the output of the 3VOUT pin is capable of driving up to 50A, but that the THRES pin input current is only in the region of 40nA. As the current drawn out of the 3VOUT pin is directly related to the receiver power consumption, the power divider resistors should have high impedance values. The sum of R1 and R2 has to be 600k in order to yield 3V at the 3VOUT pin. R1 can thus be chosen as 240k, R2 as 360k to yield an overall 3VOUT output current of 5A1 and a threshold voltage of 1.8V Note: If the LNA gain shall be kept in either high or low gain mode this has to be accomplished by tying the THRES pin to a fixed voltage. In order to achieve high gain mode operation, a voltage higher than 2.8V shall be applied to the THRES pin, such as a short to the 3VOLT pin. In order to achieve low gain mode operation a voltage lower than 0.7V shall be applied to the THRES, such as a short to ground. As stated above the capacitor connected to the TAGC pin is generating the gain control voltage of the LNA due to the charging and discharging currents of the OTA and thus is also responsible for the AGC time constant. As the charging and discharging currents are not equal two different time constants will result. The time constant corresponding to the charging process of the capacitor shall be chosen according to the data rate. According to measurements performed at Infineon the capacitor value should be greater than 47nF.
1. note the 20k resistor in series with the 3.1V internal voltage source
Wireless Components
4-3
Specification, May 2001
TDA 5211
Applications
4.2 Data Filter Design
Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1.
C1
C2
Pins: R 100k
22 R 100k
21
19
Filter_Design.wmf
Figure 4-3
Data Filter Design
(1)(2)
2Q b C1 = ---------------------R2f 3dB
with
bC2 = -------------------------4QRf 3dB
b Q = -----a
where
(3)the quality factor of the poles
in case of a Bessel filter a = 1.3617, b = 0.618 and thus Q = 0.577
and in case of a Butterworth filtera = 1.414, b = 1 and thus Q = 0.71
Example: Butterworth filter with f3dB = 5kHz and R = 100k: C1 = 450pF, C2 = 225pF
1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999
Wireless Components
4-4
Specification, May 2001
TDA 5211
Applications
4.3 Quartz Load Capacitance Calculation
The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the quartz specifications given by the quartz manufacturer.
CS Pin 28 Crystal Input impedance Z1-28
TDA5211
Pin 1
Quartz_load_5211.wmf
Figure 4-4
Determination of Series Capacitance Value for the Quartz Oscillator
Crystal specified with load capacitance
CS =
1 1 + 2 f X L Cl
with Cl the load capacitance (refer to the quartz crystal specification). Example: 10.18 MHz: CL = 12 pF XL=870 CS = 7.2 pF
This value may be obtained by putting two capacitors in series to the quartz, such as 18pF and 22pF in the 5.1MHz case and 18pF and 12pF in the 10.2MHz case.
Wireless Components
4-5
Specification, May 2001
TDA 5211
Applications
4.4 Quartz Frequency Calculation
As described in Section 3.4.3 the operating range of the on-chip VCO is wide enough to guarantee a receive frequency range between 310 and 350MHz. The VCO signal is divided by 2 before applied to the mixer . This local oscillator signal can be used to downconvert the RF signals both with high- or low-side injection at the mixer. High-side injection of the local oscillator has to be used for receive frequencies between 310 and 330 MHz. In this case the local oscillator frequency is calculated by adding the IF frequency (10.7 MHz) to the RF frequency. In this case the higher frequency of a FSK-modulated signal is demodulated as a logical one (high). Low-side injection has to be used for receive frequencies between 330 and 350 MHz. The local oscillator frequency is calculated by subtracting the IF frequency (10.7 MHz) from the RF frequency then. Please note that in this case sign-inversion occurs and the higher frequency of a FSK-modulated signal is demodulated as a logical zero (low). The overall division ratios in the PLL are 64 or 32 depending on whether the CSEL-pin is left open or tied to ground. Therefore the quartz frequency may be calculated by using the following formula: QU = (RF 10.7) / r with RF LO QU r receive frequency local oscillator (PLL) frequency (RF 10.7) quartz oscillator frequency ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table
Table 4-1 PLL Division Ratio Dependence on States of CSEL CSEL Ratio r = (fLO/fQU) 64 32
open GND This yields the following examples: CSEL tied to GND:
f QU = (315 MHz + 10 .7 MHz ) / 32 = 10 .1781 MHz f QU = (345 MHz - 10 .7 MHz ) / 32 = 10 .4469 MHz
CSEL open:
f QU = (315 MHz + 10 .7 MHz ) / 64 = 5 .0891 MHz f QU = (345 MHz - 10 .7 MHz ) / 64 = 5 .2234 MHz
Wireless Components 4-6 Specification, May 2001
TDA 5211
Applications
4.5 Data Slicer Threshold Generation
The threshold of the data slicer can be generated using an external R-C integrator as shown in Figure 4-5. The cut-off frequency of the R-C integrator has to be lower than the lowest frequency appearing in the data signal. In order to keep distortion low, the minimum value for R is 20k.
R C
Pins:
19
20 Uthreshold
data out 25
data filter data slicer
Data_slice1.wmf
Figure 4-5
Data Slicer Threshold Generation with External R-C Integrator
In case of ASK operation another possibility for threshold generation is to use the peak detector in connection with two resistors and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used.
R C R data out 25 Uthreshold
Pins: peak detector
26
19
20
data slicer
data filter
Data_slice2.wmf
Figure 4-6
Data Slicer Threshold Generation Utilising the Peak Detector
Wireless Components
4-7
Specification, May 2001
TDA 5211
Applications
4.6 ASK/FSK Switch Functional Description
The TDA5211 is containing an ASK/FSK switch which can be controlled via Pin 15 (MSEL). This switch is actually consisting of 2 operational amplifiers that are having a gain of 1 in case of the ASK amplifier and a gain of 11 in case of the FSK amplifier in order to achieve an appropriate demodulation gain characteristic. In order to compensate for the DC-offset generated especially in case of the FSK PLL demodulator there is a feedback connection between the threshold voltage of the bit slicer comparator (Pin 20) to the negative input of the FSK switch amplifier. This is shown in the following figure.
15 RSSI (ASK signal)
MSEL
ASK/FSK Switch Data Filter FSK PLL Demodulator + ASK + FSK 0.18 mV/kHz
AC
R1=100k
R2=100k v=1 + Comp
DATA Out 25
R3=300k typ. 2 V 1.5 V......2.5 V
DC
R4=30k ASK mode : v=1 FSK mode : v=11
FFB 22
21
OPP
SLP
19
20
SLN
C1 C2
R C
ask_fsk_datapath.WMF
Figure 4-7
ASK/FSK mode datapath
4.6.1
FSK Mode
The FSK datapath has a bandpass characterisitc due to the feedback shown above (highpass) and the data filter (lowpass). The lower cutoff frequency f2 is determined by the external RC-combination. The upper cutoff frequency f3 is determined by the data filter bandwidth. The demodulation gain of the FSK PLL demodulator is 140V/kHz. This gain is increased by the gain v of the FSK switch, which is 11. Therefore the resulting dynamic gain of this circuit is 1.5mV/kHz within the bandpass. The gain for the DC content of FSK signal remains at 140V/kHz. The cutoff frequencies of the bandpass have to be chosen such that the spectrum of the data signal is influenced in an acceptable amount. In case that the user data is containing long sequences of logical zeroes the effect of the drift-off of the bit slicer threshold voltage can be lowered if the offset voltage inherent at the negative input of the slicer comparator (Pin20) is used. The comparator has no hysteresis built in.
Wireless Components
4-8
Specification, May 2001
TDA 5211
Applications
This offset voltage is generated by the bias current of the negative input of the comparator (i.e. 20nA) running over the external resistor R. This voltage raises the voltage appearing at pin 20 (e.g. 1mV with R = 100k). In order to obtain benefit of this asymmetrical offset for the demodulation of long zeros the lower of the two FSK frequencies should be chosen in the transmitter as the zerosymbol frequency. In the following figure the shape of the above mentioned bandpass is shown.
gain (pin19)
v v -3dB
20dB/dec
-40dB/dec
3dB 0dB f DC f1 f2 f3
0.18m Hz V/k
2m Hz V/k
frequenzgang.WMF
Figure 4-8
Frequency characterstic in case of FSK mode
The cutoff frequencies are calculated with the following formulas:
f1 =
1 R 330k C 2 R + 330k
f 2 = v f1 = 11 f1
f 3 = f 3dB
f3 is the 3dB cutoff frequency of the data filter - see Section 4.2. Example: R = 100k, C = 47nF This leads tof1 = 44Hz and f2 = 485Hz
Wireless Components
4-9
Specification, May 2001
TDA 5211
Applications
4.6.2
ASK Mode
In case the receiver is operated in ASK mode the datapath frequency charactersitic is dominated by the data filter alone, thus it is lowpass shaped.The cutoff frequency is determined by the external capacitors C12 and C14 and the internal 100k resistors as described in Section 4.2
0dB -3dB
-40dB/dec
f f3dB
freq_ask.WMF
Figure 4-9
Frequency charcteristic in case of ASK mode
Wireless Components
4 - 10
Specification, May 2001
TDA 5211
Applications
4.7 Principle of the Precharge Circuit
In case the data slicer threshold shall be generated with an external RC network as described in Section 4.5 it is necessary to use large values for the capacitor C attached to the SLN pin (pin 20) in order to achieve long time constants. This results also from the fact that the choice of the value for R connected between the SLP and SLN pins (pins 19 and 20) is limited by the 330k resistor appearing in parallel to R as can be seen in Figure 4-7. Apart from this a resistor value of 100k leads to a voltage offset of 1mv at the comparator input as described in Section 4.6.1. The resulting startup time constant 1 can be calculated with:
1 = (R // 330k) * C
In case R is chosen to be 100k and C is chosen as 47nF this leads to
1 = (100k // 330k) * 47nF = 77k * 47nF = 3.6ms
When the device is turned on this time constant dominates the time necessary for the device to be able to demodulate data properly. In the powerdown mode the capacitor is only discharged by leakage currents. In order to reduce the turn-on time in the presence of large values of C a precharge circuit was included in the TDA5211 as shown in the following figure.
C2
R1+R2=600k R1 R2 C R Uth r es h o ld 24 23 Uc>Us U2 0 / 240uA OTA 20k +3.1V +2.4V Uc+ Us
U2<2.4V : I=240uA U2>2.4V : I=0
Figure 4-10
Principle of the precharge circuit
Wireless Components
4 - 11
+
precharge.WMF
Specification, May 2001
TDA 5211
Applications
This circuit charges the capacitor C with an inrush current Iload of typically 220A for a duration of T2 until the voltage Uc appearing on the capacitor is equal to the voltage Us at the input of the data filter. This voltage is limited to 2.5V. As soon as these voltages are equal or the duration T2 is exceeded the precharge circuit is disabled.
2 is the time constant of the charging process of C which can be calculated as 2 20k * C2
as the sum of R1 and R2 is sufficiently large and thus can be neglected. T2 can then be calculated according to the following formula:
1 T 2 = 2 ln 1 - 2 . 4V 3V (c) * 2 1 . 6
The voltage transient during the charging of C2 is shown in the following figure:
U2
3V 2.4V
2
T2
e-fkt1.WMF
Figure 4-11
Voltage appearing on C2 during precharging process
The voltage appearing on the capacitor C connected to pin 20 is shown in the following figure. It can be seen that due to the fact that it is charged by a constant current source it exhibits is a linear increase in voltage which is limited to USmax = 2.5V which is also the approximate operating point of the data filter input. The time constant appearing in this case can be denoted as T3, which can be calculated with
USmax C 2.5V T3 = ----------------------- = ---------------- C 220A 220A
Wireless Components
4 - 12
Specification, May 2001
TDA 5211
Applications
Uc
Us
T3
e-Fkt2.WMF
Figure 4-12
Voltage transient on capacitor C attached to pin 20
As an example the choice of C2 = 22nF and C = 47nF yields
2 = 0.44ms
T2 = 0.71ms T3 = 0.53ms This means that in this case the inrush current could flow for a duration of 0.64ms but stops already after 0.49ms when the USmax limit has been reached. T3 should always be chosen to be shorter than T2. It has to be noted finally that during the turn-on duration T2 the overall device power consumption is increased by the 220A needed to charge C. The precharge circuit may be disabled if C2 is not equipped. This yields a T2 close to zero. Note that the sum of R4 and R5 has to be 600k in order to produce 3V at the THRES pin as this voltage is internally used also as the reference for the FSK demodulator.
Wireless Components
4 - 13
Specification, May 2001
5
Reference
Contents of this Chapter 5.1 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
TDA 5211
preliminary
Reference
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 105C # Parameter Symbol Limit Values min 1 2 3 4 5 Supply Voltage Junction Temperature Storage Temperature Thermal Resistance ESD integrity, all pins excl. Pins 1,3, 6, 28 ESD integrity Pins 1,3,6,28 Vs Tj Ts RthJA VESD -0.3 -40 -40 max 5.5 +150 +125 114 +2 +1.5 V C C K/W kV kV HBM according to MIL STD 883D, method 3015.7 Unit Remarks
Wireless Components
5-2
Specification, May 2001
TDA 5211
preliminary
Reference
5.1.2
Operating Range
Within the operational range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed. Currents flowing into the device are denoted as positive currents and v.v.
Supply voltage: VCC = 4.5V .. 5.5V
Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 105C # Parameter Symbol Limit Values min 1 Supply Current ISF ISA RFin 3.9 3.2 max 7.5 6.8 -13 -13 mA mA dBm dBm fRF = 315MHz, FSK Mode fRF = 315MHz, ASK Mode @ source impedance 50, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth
s
Unit
Test Conditions
L
Item
2
Receiver Input Level ASK FSK, frequ. dev. 50kHz
-110 -102
3 4 5
LNI Input Frequency MI/X Input Frequency 3dB IF Frequency Range ASK FSK Powerdown Mode On Powerdown Mode Off Gain Control Voltage, LNA high gain state Gain Control Voltage, LNA low gain state
fRF fMI
310 310
350 350
MHz MHz
fIF -3dB PWDNON PWDNOFF VTHRES VTHRES
5 10.4 0 2 2.8 0
23 11 0.8 VS VS 0.7
MHz V V V V
s
6 7 8 9
s This value is guaranteed by design.
Wireless Components
5-3
Specification, May 2001
TDA 5211
preliminary
Reference
5.1.3
AC/DC Characteristics at TAMB = 25C
AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temperature range. Typical characteristics are the median of the production. Currents flowing into the device are denoted as positive currents and vice versa. The device performance parameters marked with s were measured on an Infineon evaluation board as described in Section 5.2.
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V Parameter Symbol min Supply Supply Current 1 2 Supply current, standby mode Supply current, device operating in FSK mode Supply current, device operating in ASK mode IS PDWN ISF 4.9 50 5.7 100 6.5 nA mA Pin 27 (PDWN) open or tied to 0 V Pin 11 (FSEL) open, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) open, Pin 15 (MSEL) open Limit Values typ max Unit Test Conditions L Item
3
ISA
4.2
5
5.8
mA
LNA Signal Input LNI (PIN 3), VTHRES > 2.8V, high gain mode 1 Average Power Level at BER = 2E-3 (Sensitivity) Average Power Level at BER = 2E-3 (Sensitivity) FSK Input impedance, fRF = 315 MHz Input level @ 1dB C.P. fRF=315 MHz Input 3rd order intercept point fRF = 315 MHz LO signal feedthrough at antenna port RFin -113 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth Manchester enc. datarate 4kBit, 280kHz IF Bandw., 50kHz pk. dev.
s
2
RFin
-105
dBm
s
3 4 5
S11 LNA P1dBLNA IIP3LNA LOLNI
0.895 / -25.5 deg -14 -10 dBm dBm fin = 315 & 317MHz
s
s
s
6
-119
dBm
s
Signal Output LNO (PIN 6), VTHRES > 2.8V, high gain mode 1 2 Gain fRF = 315 MHz Output impedance, fRF = 315 MHz S21 LNA S22 LNA 1.577 / 150.3 deg 0.897 / -10.3 deg
s s
Wireless Components
5-4
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min 3 4 Voltage Gain Antenna to MI fRF = 315 MHz Noise Figure GAntMI NFLNA Limit Values typ 21 2 max dB dB excluding matching network loss - see Appendix
s
Unit
Test Conditions
L
Item
s
Signal Input LNI, VTHRES = GND, low gain mode 1 2 3 Input impedance, fRF = 315 MHz Input level @ 1dB C. P. fRF = 315 MHz Input 3rd order intercept point fRF = 315 MHz S11 LNA P1dBLNA IIP3LNA 0.918 / -25.2 deg -7 -13 dBm dBm matched input fin = 315 & 317MHz
s
s
s
Signal Output LNO, VTHRES = GND, low gain mode 1 2 3 Gain fRF = 315 MHz Output impedance, fRF = 315 MHz Voltage Gain Antenna to MI fRF = 315 MHz S21 LNA S22 LNA GAntMI 0.193 / 153.7 deg 0.907 / -10.5 deg 2 dB
s s
s
Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 2.9 -3 3.1 -5 3.3 -10 V A 3VOUT Pin open see Section 4.1
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 3.3 5 VS 0.3 VS V V V nA or shorted to VCC see Section 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out ITAGC_in -3.6 1 -4.2 1.6 -5 2.2 A A RSSI > VTHRES RSSI < VTHRES
MIXER Signal Input MI/MIX (PINS 8/9) 1 2 Input impedance, fRF = 315 MHz Input 3rd order intercept point S11 MIX IIP3MIX 0.954 / -10.9 deg -25 dBm
s
s
Wireless Components
5-5
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min Signal Output IFO (PIN 12) 1 2 3 4 Output impedance Conversion Voltage Gain fRF = 315 MHz Noise Figure, SSB (~DSB NF+3dB) RF to IF isolation ZIFO GMIX NFMIX ARF-IF 330 21 13 46 dB dB dB
s s
Limit Values typ max
Unit
Test Conditions
L
Item
s
s
LIMITER Signal Input LIM/X (PINS 17/18) 1 2 3 4 Input Impedance RSSI dynamic range RSSI linearity Operating frequency (3dB points) ZLIM DRRSSI LINRSSI fLIM 5 264 60 330 396 80 dB dB 23 MHz
s s s
1
10.7
DATA FILTER 1 2 Useable bandwidth RSSI Level at Data Filter Output SLP, RFIN=-103dBm RSSI Level at Data Filter Output SLP, RFIN=-30dBm BWBB FILT RSSIlow 0.3 100 1 kHz V LNA in high gain mode LNA in high gain mode
s
3
RSSIhigh
1.8
3
V
SLICER Signal Output DATA (PIN 25) 1 2 3 Maximum Datarate LOW output voltage HIGH output voltage DRmax VSLIC_L VSLIC_H 0 VS1.3V VS-1V 100 0.1 VS0.7V kBps V V NRZ, 20pF capacitive loading
s
Slicer, Signal Output DATA (PIN 20) 1 Precharge Current Out IPCH_SLN -100 -220 -300 A see Section 4.7
Wireless Components
5-6
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 Load current Leakage current Iload Ileakage -600 0 -950 200 -1300 1000 A nA Limit Values typ max Unit Test Conditions L Item
CRYSTAL OSCILLATOR Signals CRSTL1, CRISTL 2, (PINS 1/28) 1 2 3 4 5 Operating frequency Input Impedance @ ~5MHz Input Impedance @ ~10MHz Serial Capacity @ ~5MHz Serial Capacity @ ~10MHz fCRSTL Z1-28 Z1-28 CS 5=C1 CS10=C1 5 -850 + j 625 -700 + j 865 9.7 7.2 11 MHz pF pF fundamental mode, series resonance
s
s
ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 2 ASK Mode FSK Mode VMSEL VMSEL 1.4 0 4 0.2 V V or open or tied to ground
FSK DEMODULATOR 1 2 Demodulation Gain Useable IF Bandwidth GFMDEM BWIFPLL 85 10.2 140 10.7 225 11.2 V/ kHz MHz
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 4 Powerdown Mode On Powerdown Mode Off Input bias current PDWN Start-up Time until valid IF signal is detected PWDNON PWDNOff IPDWN TSU 0 2.8 19 1 0.8 VS V V A ms Power On Mode
Wireless Components
5-7
Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol min PLL DIVIDER Signal CSEL (PIN 16) 1 2 3 fCRSTL range 5.xxMHz fCRSTL range 10.xxMHz Input bias current CSEL VCSEL VCSEL ICSEL 1.4 0 -3 -5 4 0.2 -7 V V A CSEL tied to GND or open Limit Values typ max Unit Test Conditions L Item
s Measured only in lab.
Wireless Components
5-8
Specification, May 2001
TDA 5211
preliminary
Reference
5.1.4
AC/DC Characteristics at TAMB = -40 to 105C
Currents flowing into the device are denoted as positive currents and vice versa.
Table 5-4 AC/DC Characteristics with TAMB= -40C ... + 105C, VVCC = 4.5 ... 5.5 V Parameter Symbol min Supply Supply Current 1 2 Supply current, standby mode Supply current, device operating in FSK mode Supply current, device operating in ASK mode IS PDWN ISF 3.9 50 5.7 400 7.5 nA mA Pin 27 (PDWN) open or tied to 0 V Pin 11 (FSEL) tied to GND, Pin 15 (MSEL) tied to GND Pin 11 (FSEL) open, Pin 15 (MSEL) open Limit Values typ max Unit Test Conditions L Item
3
ISA
3.2
5
6.8
mA
Signal 3VOUT (PIN 24) 1 2 Output voltage Current out V3VOUT I3VOUT 2.9 -3 3.1 -5 3.3 -10 V A 3VOUT Pin open see Section 4.1
Signal THRES (PIN 23) 1 2 3 4 Input Voltage range LNA low gain mode LNA high gain mode Current in VTHRES VTHRES VTHRES ITHRES_in 0 0 3 5 VS-1V 0.3 VS V V V nA or shorted to Pin 24 see Section 4.1
Signal TAGC (PIN 4) 1 2 Current out, LNA low gain state Current in, LNA high gain state ITAGC_out VTAGC_in -1 0.5 -4.2 1.5 -8 5 A A RSSI > VTHRES RSSI < VTHRES
MIXER 1 Conversion Voltage Gain fRF = 315 MHz GMIX +19 dB
LIMITER Signal Input LIM/X (PINS 17/18) 1 2 RSSI dynamic range RSSI Level at Data Filter Output SLP, RFIN= -103dBm RSSI Level at Data Filter Output SLP, RFIN= -30dBm DRRSSI RSSIlow 60 0.3 80 1 dB V LNA in high gain mode LNA in high gain mode
3
RSSIhigh
1.8
3
V
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Specification, May 2001
TDA 5211
preliminary
Reference
Table 5-4 AC/DC Characteristics with TAMB= -40C ... + 105C, VVCC = 4.5 ... 5.5 V Parameter Symbol min DATA FILTER Slicer, Signal Output DATA (PIN 25) 1 2 3 Maximum Datarate LOW output voltage HIGH output voltage DRmax VSLIC_L VSLIC_H 0 VS1.5V VS-1V 100 0.1 VS0.5V kBps V V NRZ, 20pF capacitive loading
s
Limit Values typ max
Unit
Test Conditions
L
Item
Slicer, Signal Output DATA (PIN 20) 1 Precharge Current Out IPCH_SLN -100 -220 -300 A see Section 4.7
PEAK DETECTOR Signal Output PDO (PIN 26) 1 2 Load current Leakage current Iload Ileakage -400 0 -850 700 -1400 2000 A nA
CRYSTAL OSCILLATOR Signals CRSTL1, CRSTL 2, (PINS 1/28) 1 Operating frequency fCRSTL 5 11 MHz fundamental mode, series resonance
ASK/FSK Signal Switch Signal MSEL (PIN 15) 1 2 ASK Mode FSK Mode VMSEL VMSEL 1.4 0 4 0.2 V V or open
FSK DEMODULATOR 1 2 Demodulation Gain Useable IF Bandwidth GFMDEM BWIFPLL 105 10.4 140 10.7 245 11 V/ kHz MHz
POWER DOWN MODE Signal PDWN (PIN 27) 1 2 3 Powerdown Mode On Powerdown Mode Off Start-up Time until valid signal is detected at IF PWDNON PWDNOff TSU 0 2.8 0.8 VS 1 V V ms
PLL DIVIDER Signal CSEL (PIN 16) 1 2 3 fCRSTL range 5.xxMHz fCRSTL range 10.xxMHz Input bias current CSEL VCSEL VCSEL ICSEL 1.4 0 -3 -5 4 0.2 -7 V V A CSEL tied to GND or open
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Specification, May 2001
TDA 5211
preliminary
Reference
5.2 Test Circuit
The device performance parameters marked with s in Section 5.1.3 were measured on an Infineon evaluation board. This evaluation board can be obtained together with evaluation boards of the accompanying transmitter device TDA5101 in an evaluation kit that may be ordered on the INFINEON RKE Webpage www.infineon.com/rke. In case a matching codeword is received, decoded and accepted by the decoder the on-board LED will turn on. This signal is also accessible on a 2-pole pin connector and can be used for simple remote-control applications. More information on the kit is available on request.
TDA521x_testboard_20_schematic.WMF
Figure 5-1
Schematic of the Evaluation Board
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Specification, May 2001
TDA 5211
preliminary
Reference
5.3 Test Board Layouts
tda521x_testboard_20_top.WMF
Figure 5-2
Top Side of the Evaluation Board
tda521x_testboard_20_bot.WMF
Figure 5-3
Bottom Side of the Evaluation Board
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Specification, May 2001
TDA 5211
preliminary
Reference
tda521x_testboard_20_plc.EMF
Figure 5-4
Component Placement on the Evaluation Board
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Specification, May 2001
TDA 5211
preliminary
Reference
5.4 Bill of Materials
The following components are necessary for evaluation of the TDA5211 at 315 MHz without use of a Microchip HCS512 decoder.
Table 5-5 Bill of Materials Ref R1 R2 R3 R4 R5 R6 L1 L2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Q1 Q2 X2, X3 Value 100k 100k 820k 240k 360k 10k 15nH 12pF 3.3 pF 10pF 6.8pF 100pF 47nF 15nH 100pF 33pF 100pF 10nF 10nF 220pF 47nF 470pF 47nF 12pF 18pF 22nF (315 + 10.7MHz)/32 SFE10.7MA5-A 142-0701-801 Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% Toko, PTL2012-F15N0G 0805,COG, 2% 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 0.1pF 0805, COG, 5% 1206, X7R, 10% Toko, PTL2012-F15N0G 0805, COG, 5% 0805, COG, 5% 0805, COG, 5% 0805, X7R, 10% 0805, X7R, 10% 0805, COG, 5% 0805, X7R, 10% 0805, COG, 5% 0805, COG, 5% 0805, COG, 1% 0805, COG, 1% 0805, X7R, 5% HC49/U, fundamental mode, CL = 12pF, e.g. 315 MHz: Jauch Q 10,178130-S11-1017-12-10/20 Murata Johnson
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Specification, May 2001
TDA 5211
preliminary
Reference
S1-S3, S6 X1 S4 IC1 TDA 5211
2-pole pin connector 3-pole pin connector, or not equipped Infineon
Please note that a capacitor has to be soldered in place L2 and an inductor in place C6.
The following components are necessary in addition to the above mentioned ones for evaluation of the TDA5211 in conjunction with a Microchip HCS512 decoder.
Table 5-6 Bill of Materials Addendum Ref R7 R8 R9 R10 R11 R12 R13 R14 R21 R22 R23 R24 R25 C19 C21 C22 IC2 S5, X4-X9 T1, T2 D1 BC 847B LS T670-JL Value 100k 10k 100k 22k 100 100 100 100 22k 10k 22k 820k 560 10pF 100nF 100nF HCS512 Specification 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, COG, 5% 1206, X7R, 10% 1206, X7R, 10% Microchip 2-pole pin connector Infineon Infineon
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Specification, May 2001
TDA 5211
preliminary
Reference
5.5 Appendix - Noise Figure and Gain Circles
The following gain and noise figure circles were measured utilizing Microlab Stub Stretchers and a HP8514 network analyser. Maximum gain is shown at point 1 at 18.5 dB, minimum noise figure ist 1.9dB at point 2, step size of circles is 0.5dB.
Figure 5-5
Gain and Noise Circles of the TDA5211 at 315 MHz.
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Specification, May 2001
TDA 5211
preliminary
Reference
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Specification, May 2001
TDA 5211
List of Figures
List of Figures
Figure 2-1 Figure 3-1 Figure 3-2 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RSSI Level and Permissive AGC Threshold Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . ASK/FSK mode datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency characterstic in case of FSK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Frequency charcteristic in case of ASK mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3-2 3-9 4-2 4-3 4-4 4-5 4-7 4-7 4-8 4-9 4-10 4-11 4-12 4-13 5-12 5-13 5-13 5-14 5-17
Figure 4-10 Principle of the precharge circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-11 Voltage appearing on C2 during precharging process . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-12 Voltage transient on capacitor C attached to pin 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Top Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain and Noise Circles of the TDA5211 at 315 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . .
Wireless Components
List of Figures - 1
Specification, May 2001
TDA 5211
List of Tables
List of Tables
Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 4-1 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MSEL Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Division Ratio Dependence on States of CSEL . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 105C . . . . . . . . Operating Range, Ambient temperature TAMB= -40C ... + 105C . . . . . . . . . . . . . . . . AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . AC/DC Characteristics with TAMB= -40C ... + 105C, VVCC = 4.5 ... 5.5 V . . . . . . . . . Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3-10 3-11 3-12 4-6 5-2 5-3 5-4 5-9 5-15 5-16
Wireless Components
List of Tables - 1
Specification, May 2001

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